1. Technical Field
A method for manufacturing a semiconductor integrated circuit is disclosed. More particularly, a method for manufacturing a capacitor of a semiconductor device is disclosed.
2. Description of the Related Art
For a DRAM (Dynamic Random Access Memory), the memory cell area memorizing a bit, the standard unit for memory information, becomes smaller as the integration increases. However, the area of a capacitor cannot be reduced in proportion to the reduction of a cell. This is because more than a certain volume of capacitance is in need per cell for sensing, signal margin, sensing speed and durability for soft error caused by alpha particles. Capacitance C is in relation with the valid surface area A of a capacitor, dielectric constant ∈ and thickness d of a dielectric substance as shown in Formula 1.
C=∈A/dxe2x80x83xe2x80x83(1)
Accordingly, to maintain the capacitance C of a capacitor in limited cell area, one should either reduce the thickness d of a dielectric substance, increase the valid surface area A of the capacitor, or use a material with a high dielectric constant ∈.
Among them, the methods of minimizing the thickness d of a dielectric substance and of increasing the valid surface area of a capacitor with a three dimensional structure, such as a simple stack structure, concave structure, cylindrical structure and multi-layer pin structure have reached their limits due to the ultra miniaturization of semiconductor manufacturing process.
A conventional dielectric layer used for a capacitor has been mainly a NO (Nitride-Oxide) or ONO (Oxide-Nitride-Oxide) thin layer. However, the current situation requires the introduction of a new material, because there is limit to increase the capacitance that is already high, even though the thickness of a dielectric substance thin layer is reduced or the surface area is increased. This is because the dielectric constant of SiO2, NO (Nitride-Oxide) or ONO (Oxide-Nitride-Oxide) layer are small.
Accordingly, high dielectric layers, e.g., (Ba,Sr)TiO3 (BST), SrTiO3 (STO), (Pb,Zr)TiO3 (PZT), (Pb,La) (Zr,Ti)O3 (PLZT), SrBi2Ta2O9 (SBT), TaON and Ta2O5 are introduced to substitute the conventional dielectric thin layer in a highly integrated DRAM.
For capacitors using high dielectric layers, it is difficult to use polysilicon as an electrode material. Instead, they use noble metals or their oxides, such as Pt, Ir, Ru, RuO2 and IrO2, or conductive compounds like TiN.
For example, in case of using Ta2O5 as a dielectric layer, MIS (Metal/Insulator/Silicon) structure or MIM (Metal/Insulator/Metal) structure should be adopted. In case of using BST, the MIM (Metal/Insulator/Metal) structure is to be employed. When forming a capacitor electrode with the metals shown above, a barrier layer of TiN, TaN, TiSiN and TaAlN should be formed necessarily to prevent the reaction between the polysilicon plug or substrate silicon and the metal, to secure the ohmic contact property, and to prevent the diffusion of oxygen, which is used as a source while a dielectric layer is deposited.
FIG. 1 is a cross-sectional view illustrating a conventional concave capacitor.
A concave capacitor and a cylinder capacitor are contrived to avoid the difficulty in etching that is caused as the height of the bottom electrode increases, in a three dimensional stack capacitor in response to the high integration tendency of a DRAM. The concave or cylinder capacity makes it possible to avoid the difficulty in etching process and control the height of a storage node.
FIG. 2 is a cross-sectional view depicting a conventional stack capacitor.
The stack structure is formed as follows. First, after the formation of an inter-layer insulation film 140 on a semiconductor substrate 100, a storage contact hole is formed and connected to an active region (not illustrated) of the semiconductor substrate through the inter-layer insulation film 140. Subsequently, a plug is molded by forming a polysilicon layer 145 and a barrier layer 165 and a silicide layer respectively. After the formation of the plug, the bottom electrode is deposited, etched selectively and thus a bottom electrode pattern 170 is formed. A stack capacitor is formed by molding a dielectric layer 180 and a top electrode 180 on the bottom electrode pattern 170 and patterning it.
When molding the bottom electrode of a simple stack capacitor with the metal as described above, there are following problems. That is, after the deposition of a metallic layer which forms the bottom electrode in the CVD (Chemical Vapor Deposition), the substrate should be etched and patterned. However, the noble metals used as a bottom electrode are hard and stable they hardly react with other chemicals, which makes them difficult to etch. It may be possible to do patterning in the reactive ion etching (RIE), but it is still difficult to obtain a desired sidewall profile with currently available etching equipment. Also, it is difficult as well to get a material for an etching mask with a lower etching degree than the noble metals. Lastly, the metallic layer deposed in the CVD has a problem that the amount of leakage current increases. This is because the surface of an electrode becomes rough by the elimination of impurities and subsequent thermal treatment, and thus the dielectric layer is not formed with a nonuniform thickness.
Therefore, a method for manufacturing a semiconductor device is disclosed in which a capacitor can be formed with a simplified process.
A method for manufacturing a semiconductor device is also disclosed in which a metallic bottom electrode can be formed in a capacitor without etching a metallic layer.
A method for manufacturing a semiconductor device is also disclosed which can suppress the generation of leakage current caused by the rough surface of a bottom electrode.
In an embodiment of the disclosed method, a method for manufacturing a semiconductor device comprises: a) forming a contact hole to expose the joining portion by etching an inter-layer insulation layer on top of a semiconductor substrate optionally; b) forming a contact plug inside the contact hole; c) molding an etch stop layer and a sacrificial oxide layer on the contact plug and the inter-layer insulation layer; d) molding a storage node hole to expose the contact plug by etching the etch stop layer and the sacrificial oxide layer optionally; e) forming a TiN bottom electrode inside the storage node hole in the CVD method; f) separating the TiN bottom electrode neighboring the sacrificial layer by removing the TiN layer thereon; g) exposing the TiN bottom electrode pattern by removing the sacrificial oxide layer; h) forming a dielectric layer on the TiN bottom electrode pattern; and molding a top electrode on the dielectric layer.